This application claims the benefit of Korean Patent Application No. 9442/1999, filed on Mar. 19, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a transistor, and more particularly, to a tri-gate MOSFET and a method for fabricating the same.
2. Background of the Related Art
Field effect transistors which have three gate electrodes disposed in a row along a channel region between source/drain have been used in research on influences of a very shallow junction in a short channel MOSFET to the short channel effect, such as a threshold voltage roll-off, and in research on hot carrier injection from an MOSFET channel. FIG. 1 illustrates a section of a first exemplary related art tri-gate transistor, and FIG. 2 illustrates a section of a second exemplary related art tri-gate transistor.
In the first exemplary related art tri-gate transistor, a bias on the side gates forms inversion layers in respective channel regions, so that the respective inversion layers connect n+ source/drain regions formed by ion implantation to a main gate channel. The inversion layers formed thus become source/drain regions having very low junction depths with respect to a main gate, and fields and potential distributions in respective channels and charge concentrations in respective inversion layers can be varied with the voltages on respective side gates. In tests studying a mechanism of hot carrier injection using a tri-gate transistor, test conditions may be varied freely by varying a main gate bias and a drain side gate bias of vertical and horizontal fields of a hot electron injection point from the channel, and by varying a current in a channel by varying a source side gate bias. If the current is regulated at a low level, parameters which influence to a hot carrier injection can be extracted by measuring gate and substrate currents while not disturbing a field distribution in the channel. The inversion layers formed by the side gate biases can be used as source/drain of an MOSFET. In this instance, the source/drain have junction depths ranging several nanometers, and the MOSFET is operative as a device having source/drain aligned exactly at rims or edges of a gate. The use of very shallow source/drain can effectively prevent the short channel effects, such as threshold voltage roll-off and DIBL (Drain Induced Barrier Lowering), which are due to the infiltration of the electric field of the MOSFET drain toward the channel. And, since it is impossible to form source/drain regions by ion implantation in a case when a size of a gate pattern in a range of several tens of a nanometer is formed by an advanced lithography, use of such an inversion layer as a form of source/drain that is aligned exactly to a gate is suggested as an alternative.
A related art tri-gate transistor will be explained with reference to the attached drawings.
Referring to FIG. 1, the related art tri-gate transistor is provided with a main gate 5 formed on a p type semiconductor substrate 1, and a gate insulating film 4 between the main gate 5 and the semiconductor substrate. And, there is a thin insulating film 6 (oxide film) formed on a surface of the main gate 5, two side gates 7 and 8 on the insulating film 6 at both sides of the main gate 5, and heavily doped n type source/drain impurity regions 2 and 3 in the semiconductor substrate 1 on both sides of the side gates 7 and 8.
And, referring to FIG. 2, another related art tri-gate transistor is provided with a main gate 5 with sloped opposite sides formed on a p type semiconductor substrate 1, and a gate insulating film 4 formed between the main gate 5 and the semiconductor substrate. And, there are a thin insulating film 6 (oxide film) formed on a surface of the main gate 5, two side gates 7 and 8 formed on the insulating film 6 at both sides of the main gate 5, heavily doped n type source/drain impurity regions 2 and 3 in the semiconductor substrate 1 on both sides of the side gates 7 and 8. A portion of each of the two side gates 7 and 8 is overlapped with the main gate 5.
A method for fabricating the aforementioned related art transistor will be explained. FIGS. 3axcx9c3c illustrate sections showing the steps of a method for fabricating a transistor.
Referring to FIG. 3a, the method for fabricating the aforementioned related art transistor starts from forming a gate insulating film 4 on a p type semiconductor substrate 1, and implanting ions into the semiconductor substrate 1 for the first time for adjusting a threshold voltage. Then, polysilicon is deposited on the gate insulating film 4 and the polysilicon and the gate insulating film 4 are selectively removed by photolithography or E-beam to form a main gate 5. As shown in FIG. 3b, the main gate 5 is used as a mask in implanting ions into the semiconductor substrate 1 for the second time for adjusting the threshold voltage. And, a thin insulating film 6 is formed on an entire surface of the substrate inclusive of the main gate 5, and polysilicon 9 is deposited on the insulating film 6. As shown in FIG. 3c, the polysilicon is subjected to anisotropic etching, to form two side gates 7 and 8 on the insulating film 6 at both sides of the main gate 5, and the main gate 5 and the two side gates 7 and 8 are used as masks in heavily implanting n type impurity ions into the semiconductor substrate, to form n type source/drain impurity regions 2 and 3.
However, the aforementioned related art tri-gate transistor has the following problems.
First, because the main gate is formed by photolithography or E-beam in the method for fabricating the related art tri-gate transistor, the length of the main gate can not be formed shorter than the limit of the lithography. Therefore, a tri-gate transistor with a very short channel length can not be fabricated.
Second, the formation of the side gates after formation of the main gate in the method for fabricating the related art tri-gate transistor leads to impurity concentrations under the side gates being equal to or higher than an impurity concentration under the main gate, always. That is, threshold voltages of MOS capacitors at the side gate sides are higher than that at the main gate side, requiring application of substantially higher voltages to the side gates for inducing an inversion layer charge adequate for operation. Thus causes a problem of insulation breakdown if the oxide film between the gates is thin.
Accordingly, the present invention is directed to a tri-gate transistor and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a tri-gate transistor and a method for fabricating the same, which allows formation of a channel length shorter than a lithography limit and a variety of substrate impurity concentration adjustments.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the transistor includes first and second side gates formed on a semiconductor substrate at sides of a trench, wherein a gap is formed between the first and second side gates, a main gate formed in and over the gap and over the first and second side gates on the semiconductor substrate, wherein the main gate is wider than the gap and overlaps the first and second side gates, an insulating film formed between the semiconductor substrate and the first side gate, second side gate, and the main gate and between the first and second side gates and the main gate, and the semiconductor substrate and between the first and second side gates and the main gate, and source/drain impurity regions formed in the semiconductor substrate on sides of the first and second side gates.
In another aspect of the present invention, there is provided a method for fabricating a transistor including the steps of (1) depositing an insulating film on a semiconductor substrate and forming a trench to expose the semiconductor substrate, (2) forming two side gates at sides of the trench, (3) forming a main gate over the semiconductor substrate between the side gates, and (4) removing the insulating film, and using the main gate and the side gates as masks in forming source/drain impurity regions in the semiconductor substrate on both sides of the side gates.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device including the steps of (1) forming an insulating film on a first conduction type semiconductor substrate, (2) selectively removing the insulating film to expose the semiconductor substrate to form a trench, (3) implanting ions into the exposed semiconductor substrate for adjusting a threshold voltage for a first time, (4) forming a first gate insulating film on a surface of the exposed semiconductor substrate, (5) forming a first and a second side gates on the first gate insulating film at sides of the trench, (6) removing the first gate insulating film between the first and second side gates, (7) injecting ions into the exposed semiconductor substrate for adjusting the threshold voltage for a second time, (8) forming a second gate insulating film on surfaces of the first and second side gates and the exposed semiconductor substrate, (9) forming a main gate on the second gate insulating film between the first and second side gates, and (10) removing the second gate insulating film and forming source/drain impurity regions in the semiconductor substrate on sides of the first and second side gates.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of (1) forming a buffer oxide film and a nitride film on a first conduction type semiconductor substrate, (2) selectively removing the buffer oxide film and the nitride film to expose the semiconductor substrate and form a trench, (3) implanting B ions into the exposed semiconductor substrate for adjusting a threshold voltage for a first time, (4) forming oxide film sidewalls at inside walls of the trench, (5) forming a first gate insulating film on a surface of the exposed semiconductor substrate, (6) forming a first and a second side gates on the first gate insulating film at sides of the trench, (7) removing the first gate insulating film between the first and second side gates, (8) injecting BF2 ions into the exposed semiconductor substrate for adjusting the threshold voltage for a second time, (9) forming a second gate insulating film on surfaces of the first and second side gates and the exposed semiconductor substrate, (10) forming a main gate on the second gate insulating film between the first and second side gates, (11) forming an oxide film on a surface of the main gate, and (12) removing the nitride film using phosphoric acid solution, and forming source/drain impurity regions in the semiconductor substrate on sides of the first and second side gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.